This time I will write about something I don't understand :-( Or at least not completely. Some time ago I was debugging a new Intel hardware platform (Adlink ETX-BT, Celeron J1900) and I experienced unexpected hangups during boot of the DEBUG version of my WINCE800 image. The RELEASE version never gave problems and started properly. After narrowing down the problem, I came across this piece of code inside PCIBUS.DLL (pcicfg.c line ±800) ... // Set the bus numbers & secondary latency // Need to ......
In Windows CE all hardware interrupts are handled by 1 Interrupt Service Routine (ISR) at the lowest level. Its main purpose is to identify the Interrupt Request (IRQ) source and handle some low level hardware clearing and resetting of the Interrupt Controller such that new interrupts can be triggered. Once the IRQ is recognized by the ISR, it is handed over to an Interrupt Service Thread (IST). This has the advantage that the hardware IRQ priority can be overruled by the IST thread priority scheduling. ......